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87
CY7C187
64K x 1 Static RAM
Features
* High speed -- 15 ns * CMOS for optimum speed/power * Low active power -- 495 mW * Low standby power -- 220 mW * TTL compatible inputs and outputs * Automatic power-down when deselected vided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C187 has an automatic power-down feature, reducing the power consumption by 56% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable (CE) LOW, while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pin will appear on the data output (DOUT) pin. The output pin stays in high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C187 utilizes a die coat to insure alpha immunity.
Functional Description
The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is pro-
Logic Block Diagram
Pin Configurations
DI INPUT BUFFER
A0 A1 A2 A3 A4 A5 NC A6 A7 DOUT WE GND
SOJ Top View
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A15 A14 A13 A12 NC A11 A10 A9 A8 DIN CE A0 A1 A2 A3 A4 A5 A6 A7 DOUT WE GND
DIP Top View
1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC A15 A14 A13 A12 A11 A10 A9 A8 DIN CE
A12 A13 A14 A15 A0 A1 A2 A3
ROW DECODER
256 x 256 ARRAY
SENSE AMPS
DO
C187-3
C187-2
CE
COLUMN DECODER POWER DOWN
WE A4 A5 A6 A7 A8 A9 A10 A11
C187-1
Selection Guide[1]
7C187-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Note: 1. For military specifications, see the CY7C187A datasheet.
7C187-20 20 80 40/20
7C187-25 25 70 20/20
7C187-35 35 70 20/20
15 90 40/20
Cypress Semiconductor Corporation Document #: 38-05044 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised August 24, 2001
CY7C187
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 22 to Pin 11) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ............................................ -0.5V to +7.0V DC Input Voltage[2] .........................................-0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
7C187-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE PowerDown Current[4] Automatic CE Power-Down Current
[2]
7C187-20 Min. 2.4 Max.
7C187-25, 35 Min. 2.4 Max. Unit V 0.4 2.2 -0.5 -5 -5 VCC 0.8 +5 +5 -350 70 20 20 V V V A A mA mA mA mA
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL =12.0 mA
Min. 2.4
Max.
0.4 2.2 -0.5 VCC 0.8 +5 +5 -350 90 40 20 2.2 -0.5 -5 -5
0.4 VCC 0.8 +5 +5 -350 80 40 20
GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE VIH Max. VCC, CE VCC - 0.3V, VIN VCC - 0.3V or VIN 0.3V
-5 -5
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
Notes: 2. VIL (min.) = -3.0V for pulse durations less than 30 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05044 Rev. **
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CY7C187
AC Test Loads and Waveforms
R1 329 (480 MIL) R1 329 (480 MIL) ALL INPUT PULSES 3.0V R2 202 (R1 255 MIL) GND 10% 90% 90% 10%
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to:
5V OUTPUT R2 202 5 pF (R1 255 MIL) INCLUDING JIG AND SCOPE
5 ns
5 ns
C187-5
(a)
(b)
C187-4
THE VENIN EQUIVALENT 167 OUTPUT 1.73V OUTPUT 125 1.90V
Military
Commercial
Switching Characteristics Over the Operating Range[6]
7C187-15 Parameter READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD WRITE CYCLE[9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[8]
7C187-20 Min. 20 Max. Unit ns 20 5 20 5 8 0 20 20 15 15 0 0 15 10 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns
Description Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid CE LOW to Low Z[7] CE HIGH to High Z
[7, 8]
Min. 15
Max.
15 3 15 3 8 0 15 15 12 12 0 0 12 10 0 5 7
CE LOW to Power Up CE HIGH to Power Down
Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05044 Rev. **
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CY7C187
Switching Characteristics Over the Operating Range[6] (continued)
7C187-25 Parameters READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
[9]
7C187-35 Min. 35 Max. Units ns 35 5 35 5 15 0 20 25 25 25 0 0 20 15 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns
Description Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid CE LOW to Low Z
[7] [7, 8]
Min. 25
Max.
25 5 25 5 10 0 20 20 20 20 0 0 15 10 0 5 7
CE HIGH to High Z
CE LOW to Power Up CE HIGH to Power Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z
[8]
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C187-6
Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE = VIL.
Document #: 38-05044 Rev. **
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CY7C187
Switching Waveforms
Read Cycle No. 2[10, 12]
tRC CE tACE tLZCE DATA OUT HIGH IMPEDANCE DATA VALID tPD ICC 50% 50% ISB
C187-7
tHZCE
HIGH IMPEDANCE
VCC SUPPLY CURRENT
tPU
Write Cycle No. 1 (WE Controlled)[11]
tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
C187-8
tAW tPWE
tHA
tHD
tLZWE HIGH IMPEDANCE
Write Cycle No. 2 (CE Controlled)
[11, 13]
tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA VALID tHD tHA tSCE
DATA OUT
Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
HIGH IMPEDANCE
C187-9
Document #: 38-05044 Rev. **
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CY7C187
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 I CC NORMALIZED I CC, I SB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 VCC =5.0V VIN =5.0V I CC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
VCC =5.0V 0.8 0.6 -55
25
125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT SINK CURRENT (mA)
OUTPUT VOLTAGE (V)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE NORMALIZED t AA (ns) 3.0
PO
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED I CC 25.0 20.0 15.0 10.0 5.0 VCC =4.5V TA =25C 1.25
NORMALIZED I CC vs.CYCLE TIME VCC =5.0V TA =25C VCC =0.5V 1.00
2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0
NORMALIZED I
0.75
0.0
0
200
400
600
800 1000
0.50 10
20
30
40
SUPPLY VOLTAGE(V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05044 Rev. **
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CY7C187
Address Designators
Address Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Address Function X3 X4 X5 X6 X7 Y7 Y6 Y2 Y3 Y1 Y0 Y4 Y5 X0 X1 X2 Pin Number 1 2 3 4 5 6 7 8 14 15 16 17 18 19 20 21
Truth Table
CE H L L WE X H L Input/Output High Z Data Out Data In Read Write Mode Deselect/Power-Down
Ordering Information[14]
Speed (ns) 15 20 25 35 Ordering Code CY7C187-15PC CY7C187-15VC CY7C187-20PC CY7C187-20VC CY7C187-25PC CY7C187-25VC CY7C187-35PC CY7C187-35VC
Note: 14. For military variations, see the CY7C187A datasheet.
Package Name P9 V13 P9 V13 P9 V13 P9 V13
Package Type 22-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 22-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 22-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 22-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ
Operating Range Commercial Commercial Commercial Commercial
Document #: 38-05044 Rev. **
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CY7C187
Package Diagrams
22-Lead (300-Mil) Molded DIP P9
51-85012-A
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
Document #: 38-05044 Rev. **
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C187
Document Title: CY7C187 64K x 1 Static RAM Document Number: 38-05044 REV. ** ECN NO. 107146 Issue Date 09/10/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00038 to 38-05044
Document #: 38-05044 Rev. **
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